About Me

I am a Master’s student in Computer Engineering at Virginia Tech with an interest in digital design and computer architecture. My recent work centers on FPGA design and verification, and at the BRICC Lab I’ve been able to apply these skills in research projects that connect academic ideas with practical hardware implementations.

This website is a space where I share my progress: documenting the projects I work on, the challenges I tackle, and the research I’ve been contributing to at the lab. My goal is to make it both a record of my learning journey and a resource for others interested in digital design and hardware systems.

My Recent Work

I’ve been writing a 3-part blog series on designing and testing a UART-based communication system on FPGA (Zynq ZC702 board). The series walks through RTL design, simulation, and PS–PL integration using Vitis, providing a complete workflow from theory to on-board validation.

• Post 1: Designing a UART based communication system
• Post 2: Verification & On-board Testing of UART RTL
• Post 3: PS–PL Integration (Vitis Setup + Testing)

Together, these posts explain UART fundamentals, FSM-based TX/RX design, verification with testbenches, hardware loopback testing, and full PS–PL integration using Xilinx Vitis. They’re meant as a practical guide for anyone interested in FPGA-based digital design and embedded system integration.